systolic arrays

lec1 introduction

lec2 tradeoffs

lec3 combinational logic design

Basic logic gates (AND, OR, NOT, NAND, NOR, XOR) Decoder Multiplexer Full Adder Programmable Logic Array (PLA) Comparator Arithmetic Logic Unit (ALU) Tri-State Buffer

Standard form representations: SOP & POS Logical completeness Logic simplification via Boolean Algebra

lec4 sequential logic design

combinational rest

sequential

lec5a sequential logic design n fsm

seq logic design

lec5b hdl and verilog

HDL

lec6a hdl and verilog

HDL

lec6b timing and verification

timing

lec6c verification and testing

circuit verification

lec7 von neumann model